Assistant Professor

Dr Rituparna Choudhury

Department of Electronics and Communication Engineering

Interests

  • FPGA implementation of machine learning algorithms
  • ASIC implementation of machine learning algorithms

Faculty Details

Education

2015

Kalinga Institute of Industrial Technology, Bhubaneswar
India
BTech

2017

National Institute of Technology, Meghalaya
India
MTech

2023

Indian Institute of Technology, Guwahati
India
PhD

Research Interest

  • Designing of decision tree training accelerators for FPGA and ASIC.
  • Designing of decision tree classification accelerators for FPGA and ASIC

    • Memberships

  • IEEE – 2021-2022

    • Publications

  • R. Choudhury, S. R. Ahamed and P. Guha, Training Accelerator for Two Means Decision Tree, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, issue no. 7, pp. 1465-1469, July 2021.
  • R. Choudhury, S. R. Ahamed and P. Guha, FPGA Implementation of Batch-Mode Depth-Pipelined Two Means Decision Tree, in IEEE Embedded Systems Letters, vol. 15, issue no. 1, pp. 17-20, March 2023.
  • R. Choudhury, S. R. Ahamed, and P. Guha, Efficient Hardware Implementation of Decision Tree Training Accelerator, in SN Computer Science, vol. 2, issue no. 5, pp. 1-10, September 2021.
  • R. Choudhury, S. R. Ahamed and P. Guha, Hardware Implementation of Low Complexity High-speed Perceptron Block, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 26-30.
  • R. Choudhury, S. R. Ahamed and P. Guha, FPGA Implementation of Low Complexity Hybrid Decision Tree Training Accelerator, 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Lansing, MI, USA, 2021, pp. 511-514.
  • R. Choudhury, S. R. Ahamed and P. Guha, Efficient Hardware Implementation of Decision Tree Training Accelerator, 2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2020, pp. 212-215.
  • R. Choudhury, P. Rangababu, Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder, VLSI Design and Test 2017.

    • Contact Details

    • E-mail id: rituparna.c@srmap.edu.in
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