Reconceiving the building blocks of the Universe
The research at the Department of Physics is currently focusing on developing new theoretical frameworks to revamp the fundamental concepts that describe the origin of the universe. Assistant Professor Dr Amit Chakraborty has published a paper titled Revisiting Jet Clustering Algorithms for New Higgs Boson Searches in the Hadronic Final States in the European Physical Journal C, with an Impact Factor of 4.59.
Abstract
Displaced signatures originating from the pair production of a supersymmetric particle, called sneutrino, at the Large Hadron Collider (LHC) are studied. The theoretical model considered in this work is the Next-to-Minimal Supersymmetric Standard Model supplemented with right-handed neutrinos triggering a Type-I seesaw mechanism. The research has shown how such signatures can be established through a heavy Higgs portal when the sneutrinos are decaying to charged leptons and charginos giving rise to further leptons or hadrons. The research also illustrated how the Yukawa parameters of neutrinos can be extracted by measuring the lifetime of the sneutrino from the displaced vertices, thereby characterising the dynamics of the underlying mechanism of neutrino mass generation.
Explanation of the research
The Standard Model of Particle Physics is currently the remarkably successful theory to describe the basic building blocks of the universe and their interactions with the three fundamental forces of nature. Despite its success at explaining the universe, the Standard Model does have several limitations. For example, how neutrinos get their mass, why the mass spectrum of the different elements of SM fermions, namely quarks and leptons, are so hierarchical, why the Higgs boson mass is so low, etc. The primary research is to understand these issues and then propose theoretical models which circumvent these shortcomings of SM and provide signatures that can be tested in the ongoing or future proposed experiments.
For this research project, Dr Amit Chakraborty have collaborated with Particle Physics Department, STFC Rutherford Appleton Laboratory, UK and School of Physics and Astronomy, University of Southampton, UK. His broad research interest is to perform theoretical studies of physics beyond the Standard Model (BSM) in particular, collider search strategies and prospects of different BSM models at the Large Hadron Collider (LHC) and future proposed collider experiments. He aims to build new theoretical models, develop new techniques/tools, and devise new search strategies to improve our knowledge of the standard model as well as BSM physics processes.
Dr Amit Chakraborty’s future research topics include Higgs Boson Physics and Beyond Standard Model Physics Phenomenology, Dark Matter at the Colliders, Interpretable Machine Learning techniques in BSM Physics, and Ultra-light particles and Physics Beyond the Colliders.
- Published in Departmental News, News, Physics News, Research News
An IoT- based smart wallet prototype
Dr Sonam Maurya, and her research team; Soha Muskaan Sayyad, Trisha Chilukuri, Samah Maaheen Sayyad, and Juhita Naga Priya Velagapudi from the Department of Computer Science and Engineering have innovated a smart wallet model based on IoT and got their patent “Smart Wallet with Enhanced Features for Preventing Misuse and Alarm System for the Same” published. This is a fitting solution to protect against the loss and theft of the wallet.
A smart wallet is an excellent technology to safeguard your credit and debit cards. Wallets these days are getting smarter with the latest technologies induced to monitor its presence. The proposed IoT- based wallet model is more smart, intelligent, secure, and safe which encompasses the best use of the latest IoT technologies in our pocket. The prototype consists of fingerprinting access technology, Augmented Reality (AR) navigation, Interactive Air Display (IAD)/ Transparent Display (TD), Voice control mechanism, Emergency alerts, RFID features, and many more. The smart wallet is designed to overcome the shortcomings of the regular wallet types.
The new technology of AR makes the tracking of the wallet easier with a graphical pathway. And the voice control functionalities help the user to make the process easier in comparison to manual opening. IAD/ TD is used to control the mechanisms like opening the card or money case. To keep the data more secure from hackers, an RFID technology-enabled card is also embedded in the wallet. The strong Graphene outer covering is used to make the materials inside more flexible and safer. Besides, there is an emergency voice control mechanism that takes the instruction from the user and makes the surroundings alert by sending an alert message to the emergency contacts. And the cash counting facility in the wallet to keep track of the cash makes it a wholesome package of digital innovation.
The social implications of this smart wallet are:
• Enhanced features for preventing wallet misuse
• Alarm system to help in emergencies and threatening situations
• Best use of IoT technology in a user-friendly way
• Enabled with Wallet/ Card missing notifications
• Eco-friendly charging mechanism
With this innovation, the research team aims to bring technology to its fullest use to make significant transformations in the everyday life of society.
- Published in CSE NEWS, Departmental News, News, Research News
Design methodologies for composite structures in aircraft engines
Dr Prakash Jadhav, Professor and Head, Department of Mechanical Engineering at SRM University-AP has published a chapter titled “Design Methodologies for Composite Structures in Aircraft Engines” in the book Advanced composites in aerospace engineering applications, Feb 2022, ISBN 978-3-030-88191-7, Springer.
Abstract of the book chapter
Recently there have been many successful attempts to implement the use of fibre-reinforced composite structures in commercial aircraft engines. The author has been part of these efforts while working in the aviation industry. This article describes these efforts to design, analyze, manufacture, and implement the composite structures inside the low-pressure and low-temperature zones of the engine. Very innovative out-of-the-box design methodologies were used to design these components. These efforts elaborate on the design, optimization, and improvement of the composite fan blade, the composite fan platform, and the composite booster blade inside the engine. It focuses on structural design, aerodynamic efficiency, and specific fuel consumption improvement efforts along with the usual reduction of weight targets. This work successfully demonstrates the systematic steps in the design and implementation like preliminary coupon-level simulations, coupon-level manufacturing, coupon/prototype testing, and final part-level simulations followed by part tests.
The target readers for the book are all engineers, professionals and researchers from the aerospace field. Dr Prakash Jadhav’s future research plan is to continue to develop new methodologies to implement more composites into the aerospace industry. The book chapter will be extremely useful for engineers working on the design of composite structures for aerospace applications.
- Published in Departmental News, Mechanical Engineering NEWS, News, Research News
Research article accepted for IEEE conference IEMTRONICS 2022
SRM University-AP preserves a research-empowered ecosystem stimulating its faculty and students to roll out original and discerning studies capable of making instrumental contributions aiming the scientific and societal progress. Making strides with impactful research publications and groundbreaking achievements, the institution has carved a niche for itself in the academic milieu. We are glad to present yet another success story of our research community that keeps bringing laurels to the institutions from far and wide.
Dr Pradyut Kumar Sanki and his PhD scholar Bevara Vasudeva, from the Department of Electronics and Communications Engineering, along with a group of Computer Science and Engineering students: Medarametla Depthi Supriya, Devireddy Vignesh, Peram Bhanu Sai Harshath, and Sravya Kuchina have got their paper titled ‘’VLSI Implementation of a Real-Time Modified Decision-Based Algorithm for Impulse Noise Removal’’ accepted in the IEEE conference IEMTRONICS 2022. This publication is a part of the Capstone project contributed by the students.
IEMTRONICS 2022 (International IOT, Electronics and Mechatronics Conference) is an international conclave that aims to bring together scholars from different backgrounds to disseminate inventive ideas in the fields of IOT, Electronics and Mechatronics. The conference will also promote an intense dialogue between academia and industry to bridge the gap between academic research, industry initiatives, and governmental policies. This is fostered by panel discussions, invited talks, and industry exhibits where academia and industry will mutually benefit from each other.
Through the research paper, the team proposes a real-time impulse noise removal (RTINR) algorithm and its hardware architecture for denoising images corrupted with fixed valued impulse noise.
Abstract of the Research
A decision-based algorithm is modified in the proposed RTINR algorithm where the corrupted pixel is first detected and is restored with median or previous pixel value depending on the number of corrupted pixels in the image. The proposed RTINR architecture has been designed to reduce the hardware complexity as it requires 21 comparators, 4 adders, and 2 line buffers which in turn improve the execution time. The proposed architecture results better in qualitative and quantitative performance in comparison to different denoising schemes while evaluated based on the following parameters: PSNR, IEF, MSE, EKI, SSIM, FOM, and visual quality. The proposed architecture has been simulated using the XC7VX330T-FFG1761 VIRTEX7 FPGA device and the reported maximum post place and route frequency is 360.88 MHz. The proposed RTINR architecture is capable of denoising images of size 512 × 512 at 686 frames per second. The architecture has also been synthesized using UMC 90 nm technology where 103 mW power is consumed at a clock frequency of 100 MHz with a gate count of 2.3K (NAND2) including two memory buffers.
- Published in CSE NEWS, Departmental News, ECE NEWS, News, Research News