Assistant Professor

Dr Md Najrul Islam

Department of Electronics and Communication Engineering

Interests

  1. Hardware accelerator for AI applications
  2. Post quantum cryptography
  3. Low power VLSI circuits

Faculty Details

Education

2016

Tripura Institute of Technology
India
B.E

2018

NIT Meghalaya
M.Tech

2024

IIT Mandi
PhD

Research Interest

  • VLSI-Algorithm Design of Convolutional-Neural-Network (CNN) Hardware Accelerator for Edge Application.
  • Digital VLSI-Architecture Design of Efficient Neural-Network inference engine for Edge Applications.
  • Application-Specific Integrated Circuit (ASIC) Chip Design, Implementation, Testing and Field-Programmable Gate Array (FPGA) prototyping for digital processing tasks in Artificial Intelligence, Post Quantum cryptography, Encryption accelerators, High Efficiency Video Codec, Wireless Communication System, Power Electronics, and Computer Arithmetic.
  • Testing of Neural-Network inference engine by developing a test-bed based on practical object classification scenario using FPGA and ASIC platform & software environment.

Memberships

  • Member, Institute of Electrical and Electronics Engineers (IEEE).

Awards & Fellowships

  • 2024 - VLSID Fellowship, awarded with IEEE VLSID-2024 fellowship to attend tutorials and main conference at 37th IEEE International Conference on VLSI Design and 23rd International Conference on Embedded systems, Kolkata, India, Jan 5-10, 2024.
  • 2023 - VLSID Fellowship, awarded with IEEE VLSID-2023 fellowship to attend tutorials and main conference at 36nd IEEE International Conference on VLSI Design and 22th International Conference on Embedded systems, Hyderabad, India, Jan 8-12, 2023.
  • 2019 - MHRD HTRA fellowship to persue PhD from IIT Mandi
  • 2016 - GATE Fellowship , Received full fellowship to pursue M.Tech from NIT Meghalaya

Publications

  • Md. Najrul Islam, Rahul Shrestha, and Shubhajit Roy Chowdhury, “Energy-Efficient and High-Throughput CNN Inference Engine based on Memory-Sharing and Data-Reusing for Edge Applications", IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), (Early Access). DOI: 10.1109/TCSI.2024.3392807, web link
  • Md. Najrul Islam, Rahul Shrestha, and Shubhajit Roy Chowdhury, “An Uninterrupted Processing Technique Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol-30, issue-12, pp-1891-1901, Dec. 2022 DOI: 10.1109/TVLSI.2022.3210963, web link.
  • Farhana Begum, Sandeep Mishra, Md. Najrul Islam, and Anup Dandapat, “A 10-bit 2.33 fJ/conv. SAR-ADC with high speed capacitive DAC switching using a novel effective asynchronous control circuitry,” Analog Integrated Circuits and Signal Processing, DOI: 10.1007/s10470-019-01450-w, Volume: 100, Issue: 3, pp. 221-235, April-2019, web link.
  • Farhana Begum, S. Mishra, Md. Najrul Islam, and A. Dandapat,, “Frequency Improvement of 10-bit SAR-ADC using TSPC based Control Circuitry”, IEEE VLSI Circuits & Systems Letter (VCAL), Vol-5, issue-1, pp-1-8, 2019. web link.
International Conferences
  • Md. Najrul Islam, Rahul Shrestha, and Shubhajit Roy Chowdhury, “A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 414-417 (DOI: 10.1109/ISVLSI54635.2022.00093), July-2022, Cyprus (Nicosia), web link.
  • Md. Najrul Islam, Rahul Shrestha, and Shubhajit Roy Chowdhury, “Low-Complexity Classification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator," IEEE International Conference on VLSI Design and Embedded Systems (VLSID), pp. 210-215, (DOI: 10.1109/VLSID60093.2024.00041), Jan 2024, Kolkata, India, web link.
  • F. Begum, M. N. Islam, K. A. Ahmed, and K. K. Sharma, “A Compact 3 GHz Comparator for SAR-ADCs In Robotic Prosthetic Hand Designs", 10th International Conference on Microelectronics, Circuits and Systems, Guwahati, India, 2023
  • F. Begum, S. Mishra, M. N. Islam, and A. Dandapat, Analysis and Proposal of a Flash Subranging ADC Architecture. 3rd International Conference on Microelectronics, Computing and Communication Systems, pp. 283-290. March 2018.
Book Chapters
  • Farhana Begum, Sandeep Mishra, Md. Najrul Islam & Anup Dandapat,, “Analysis and Proposal of a Flash Subranging ADC Architecture,” Lecture Notes in Electrical Engineering, DOI: 0.1007/978-981-13-7091-5_26, Volume: 556 , Issue: 3, pp. 283-290, May-2019, web link.

Contact Details

TOP