Assistant Professor

Dr Arun Kumar

Department of Electronics and Communication Engineering

Interests

  1. Computational Nanoelectronics
  2. Semiconductor device modelling
  3. Reliability analysis of emerging semiconductor devices

Faculty Details

Education

2014

RTM Nagpur University
B.E.

2020

Indian Institute of Technology
Patna
Ph.D.

Experience

  • July 2017 - December 2017 | Teaching Assistant for Basic Electrical Sciences | IIT, Patna
  • January 2018 - April 2018 | Teaching Assistant for Analog Electronics Lab | IIT, Patna

Research Interest

  • Compact model development for classical and non-classical transistor architecture
  • Simulation of nanoscale and emerging transistor architectures
  • Computational Nanoelectronics
  • Reliability analysis of MOS devices
  • Modeling of quantum effects in nanoscale devices

Awards & Fellowships

  • 2015- Qualified CSIR-NET (JRF) with All India Rank-139
  • 2014, 2015- Qualified Graduate Aptitude Test in Engineering
  • 2016-2018, Junior Research Fellowship for PhD- CSIR, Government of India.
  • 2018-2020, Senior Research Fellowship for PhD- CSIR, Government of India.
  • 2019- International Travel Grant for 14th NMDC at Stockholm, Sweden- Science and Engineering Research Board (SERB), Government of India.
  • 2019- International Travel Grant for 9th INEC at Kuching, Malaysia - Council of Scientific and Industrial Research (CSIR), Government of India.
  • 2019- First position in Poster Presentation- Research Scholars’ Day, Indian Institute of Technology Patna.
  • 2014 - University order of merit in B.E. Final Exam.

Memberships

  • Member, IEEE

List of Publications

    • Arun Kumar, Shiv Bhushan, and Pramod Kumar Tiwari, “A Threshold Voltage Model of Silicon- Nanotube Based Ultra-Thin Double Gate-All-Around (DGAA) MOSFETs Incorporating Quantum Confinement Effects,” IEEE Transactions on Nanotechnology, vol. 16, no. 5 , pp 868-875, Sept. 2017.
    • Arun Kumar, Shiv Bhushan, and Pramod Kumar Tiwari, “Analytical modeling of subthreshold characteristics of ultra-thin double gate-all-around (DGAA) MOSFETs incorporating quantum confinement effects,” Superlattices and Microstructures, vol. 109, pp. 567-578, May 2017.
    • Arun Kumar, Pramod Kumar Tiwari “An Explicit Unified Drain Current Model for Silicon-Nanotube- Based Ultrathin Double Gate-All-Around MOSFETs” IEEE Transactions on Nanotechnology, vol. 17, no. 6, pp. 1224-1234, Nov. 2018.
    • Arun Kumar, Shiv Bhushan, and Pramod Kumar Tiwari “Drain current modeling of double gate-all- around (DGAA) MOSFETs”, IET Circuits, Devices & Systems, vol. 13, no. 4, pp. 519-525, July 2019.
    • Arun Kumar, P.S.T.N. Srinivas, and Pramod Kumar Tiwari, “An Insight into Self-heating Effects and its Implications on Hot Carrier Degradation for Silicon-Nanotube-based double gate-all-around (DGAA) MOSFETs,” IEEE Journal of Electron Devices Society, vol. 7, pp. 1100-1108, Nov. 2019.
    • Arun Kumar, P S T N Srinivas, S. Bhushan, S Dubey, Y K Singh, and P. K. Tiwari “Threshold Voltage Modeling of Double Gate-All-Around Metal-Oxide-Semiconductor Field-Effect-Transistors (DGAA MOSFETs) Including the Fringing Field Effects”, Journal of Nanoelectronics and Optoelectronics, Vol. 14, pp. 1–10, Nov. 2019.
    • P.S.T.N. Srinivas, Arun Kumar, and Pramod Kumar Tiwari, “A Threshold Voltage Model of Tri-Gate Schottky-Barrier (TGSB) Field-Effect-Transistors (FETs)” Silicon, 2020, https://doi.org/10.1007/s12633-020- 00400-w.
    • P.S.T.N. Srinivas, Arun Kumar, and Pramod Kumar Tiwari, “Self-heating Effects and Hot Carrier Degradation in In0.53Ga0.47As Gate-All-Around (GAA) MOSFETs” Semiconductor Science and Technology, Vol. 35, pp. 065008-1-8, May 2020.
    • Arun Kumar, P.S.T.N. Srinivas, and Pramod Kumar Tiwari, " Analytical Threshold Voltage Model of Schottky-source/drain (Schottky-S/D) double gate-all-around (DGAA) Field-Effect-Transistors (FETs),” 2019 IEEE Devices for Integrated Circuit (DevIC), Kalyani, March 2019.
    • Arun Kumar, P.S.T.N. Srinivas, and Pramod Kumar Tiwari, “Physical Insight into Self-heating Effects in Ultra-thin Junctionless Gate-All-Around FETs,” 9th IEEE International Nanoelectronics Conference (INEC), Kuching, Malaysia, July 2019.
    • Arun Kumar, P.S.T.N. Srinivas, and Pramod Kumar Tiwari, “Compact Drain Current Model of Silicon- Nanotube-based Double Gate-All-Around (DGAA) MOSFETs Incorporating Short Channel Effects,” 14th IEEE Nanotechnology Materials and Devices Conference (NMDC), Stockholm, Oct. 2019.
    • Shiv Bhushan, Arun Kumar, Deepti Gola, and Pramod Kumar Tiwari, “An analytical subthreshold current model of short-channel symmetrical double gate-all- around (DGAA) field-effect-transistors” 2017 Device for integrated circuits (DevIC), Kalyani, March 2017.
    • P.S.T.N. Srinivas, Arun Kumar, and Pramod Kumar Tiwari, “Effects of Lateral Spreading in 2- Dimensional Non-Uniform Doped Junctionless FinFETs,” 9th IEEE International Nanoelectronics Conference (INEC), Kuching, Malayisia, July 2019.
    • Pramod Kumar Tiwari, Arun Kumar, and Dipankar Talukdar, "An analytical gate tunneling current model of Re-S/D SOI MOSFETs,” 2016 IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON), Varanasi, Dec. 2016.
    • Arun Kumar, P.S.T.N. Srinivas, and Pramod Kumar Tiwari, “Analytical Modeling of Subthreshold Current and Subthreshold Swing of Schottky-Barrier Source/Drain Double Gate-All-Around (DGAA) MOSFETs” 5th IEEE International Symposium on Smart Electronic Systems (iSES), Rourkela, Dec. 2019.

     

Contact Details

TOP