Assistant Professor

Dr Manas Ranjan Tripathy

Electronics & Communication Engineering

Interests

  1. Modelling and Simulation of Advanced Transistors and their Circuit Level Applications.
  2. Memory Design using Transistors (SRAM and DRAM)
  3. Neuromorphic Computing with Memristors

Faculty Details

Education

2007

Biju Patnaik University of Technology
Rourkela
BTech

2014

SOA University
Bhubaneswar
MTech

2020

IIT BHU
Varanasi
PhD

Experience

  • Sep 2022 to May 2023 - Associate Professor - Department of ECE, SOA University, Bhubaneswar
  • July 2020 to Sep 2022 - Assistant Professor - Department of ECE, SOA University, Bhubaneswar
  • Aug 2014 to July 2017 - Assistant Professor - Department of ECE, SOA University, Bhubaneswar
  • Feb 2010 to July 2014 - Lecturer - Department of ECE, SOA University, Bhubaneswar
  • Jan 2009 to Feb 2010 - Lecturer - Department of ECE, Balasore College of Engineering and Technology, Balasore, Odisha
  • Feb 2008 to Dec 2008 - Lecturer (Contractual basis) - Department of Instrumentation and Electronics Engineering, Odisha University of Technology and Research, Bhubaneswar

Research Interest

  • Simulation and Modelling of advanced transistors like FinFETs, TFETs, etc., and their circuit-level applications in analog and digital domains.
  • SRAM and DRAM design with advanced transistors such as TFETs, FinFETs, etc.
  • Memristors and their applications in neuromorphic computing.

Awards & Fellowships

  • 2020 – Best Paper Award [Academia] in IEEE CONECCT 2020 – IEEE Bangalore Section
  • 2017- University Gold Medal for Best academic performance in Master of Technology in Electronics Engineering for the academic year 2013-2014 of ITER (Faculty of Engineering and Technology), SOA University– SOA University

Memberships

  • IEEE Member
  • IEEE Student Member 2019
  • IEEE MTT Student Member 2019

Publications

Journal Publications
  1. Design and Performance Assessment of HfO2/SiO2 Gate Stacked Ge/Si Heterojunction TFET on SELBOX Substrate (GSHJ-STFET)- A. K. Singh, M. R. Tripathy, K. Baral, and S. Jit - Silicon, 14(17), 11847-11858 (2022)
  2. GaSb/GaAs Type-II Heterojunction TFET on SELBOX Substrate for Dielectric Modulated Label-Free Biosensing Application – A. K. Singh, M. R. Tripathy, K. Baral, and S. Jit - IEEE Transactions on Electron Devices, 69 (9), 5185-5192 (2022)
  3. Deep Insight into DC/RF and Linearity Parameters of a Novel Back Gated Ferroelectric TFET on SELBOX Substrate for Ultra Low Power Applications- A. K. Singh, M. R. Tripathy, P. K. Singh, K. Baral, S. Chander, and S. Jit - Silicon, 13 (8), 3853-3863 (2021).
  4. Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis- K. Baral, P. K. Singh, G. Kumar, A. K. Singh, M. R. Tripathy, S. Kumar, and S. Jit - Materials Science in Semiconductor Processing, 133 (3), 105966 (2021)
  5. Lateral and Vertical Gate Oxide Stacking Impact on Noise Margins and Delays for the 8T SRAM Designed with Source Pocket Engineered GaSb/Si Heterojunction Vertical TFET: A Reliability Study- M. R. Tripathy, and S. Jit - IEEE Transactions on Device and Materials Reliability, 21 (3), 372-378 (2021)
  6. Analytical Drain Current Model for Source Pocket Engineered Stacked Oxide SiO 2 /HfO 2  Cylindrical Gate TFETs- P. K. Singh, K. Baral, S. Kumar, M. R. Tripathy, A. K. Singh, R. K. Upadhyay, S. Chander, and S. Jit - Silicon, 13, 1731–1739 (2021)
  7. Impact of Interface Trap Charges on Electrical Performance Characteristics of a Source Pocket Engineered Ge/Si Heterojunction Vertical TFET with HfO 2 /Al 2 O 3 Laterally Stacked Gate Oxide- M. R. Tripathy, A Samad, A. K. Singh, P. K. Singh, K. Baral, A. K. Mishra, and S. Jit - Microelectronics Reliability, 119 (4), 114073 (2021)
  8. Simulation Study and Comparative Analysis of Some TFET Structures with a Novel Partial-Ground-Plane (PGP) Based TFET on SELBOX Structure- A. K. Singh, M. R. Tripathy, S. Chander, K. Baral, P. K. Singh, and S. Jit - Silicon, 12, 2345–2354 (2020)
  9. Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate- A. K. Singh, M. R. Tripathy, K. Baral, P. K. Singh, and S. Jit - Appl. Phys. A, 126, 681 (2020)
  10. Au nanoparticles modified CuO nanowire electrode based non-enzymatic glucose detection with improved linearity- A. K. Mishra, D. K. Jarwal, B. Mukherjee, A. Kumar, S. Ratan, M. R. Tripathy, and S. Jit - Scientific Report, 10, 11451 (2020)
  11. Impact of Heterogeneous Gate Dielectric on DC, RF and Circuit-Level Performance of Source-Pocket Engineered Ge/Si Heterojunction Vertical TFET- M. R. Tripathy, A. K. Singh, A Samad, P. K. Singh, K. Baral, and S. Jit - Semiconductor Science and Technology, 35, 105014 (2020)
  12. A 2-D compact DC model for engineered nanowire JAM-MOSFETs valid for all operating regimes- K. Baral, P. K. Singh, S. Kumar, M. R. Tripathy, A. K. Singh, S. Chander, and S. Jit - Semiconductor Science and Technology, 35, 085014 (2020)
  13. Investigation of DC, RF and linearity performances of a back-gated (BG) heterojunction (HJ) TFET-on-selbox-substrate (STFET): Introduction to a BG-HJ-STEFT based CMOS inverter- A. K. Singh, M. R. Tripathy, K. Baral, P. K. Singh, and S. Jit - Microelectronics Journal, 102, 104775 (2020)
  14. III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications- M. R. Tripathy, A. K. Singh, A Samad, S. Chander, K. Baral, P. K. Singh, and S. Jit - Superlattices and Microstructures, 142, 106494 (2020)
  15. Source pocket engineered underlap stacked oxide cylindrical gate tunnel FETs with improved performance: design and analysis- P. K. Singh, K. Baral, S. Kumar, S. Chander, M. R. TripathyA. K. Singh, and S. Jit - Applied Physics A, 126 (2020)
  16. Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications- M. R. Tripathy, A. K. Singh, A Samad, S. Chander, K. Baral, P. K. Singh, and S. Jit - IEEE Transactions on Electron Devices, 67 (3), 1285-1292 (2020)
  17. 2-D analytical modeling of drain and gate-leakage currents of cylindrical gate asymmetric halo doped dual material-junctionless accumulation mode MOSFET- K. Baral, P. K. Singh, S. Kumar, A. K. Singh, M. R. Tripathy, S. Chander, and S. Jit - AEU - International Journal of Electronics and Communications, 116, 153071 (2020)
  18. Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs- S. Chander, S. Baishya, S. K. Sinha, S. Kumar, P. K. Singh, K. Baral, M. R. Tripathy, A. K. Singh, and S. Jit - Superlattices and Microstructures, 131, 30–39 (2019)
Conferences
  1. Design and Simulation of Triple Material Gate InAs/Si Heterojunction TFET on SEL-BOX Substrates: Temperature Impact Analysis- A. K. Singh, M. R. Tripathy, R. K. Upadhyay, and S. Jit- 2021 IEEE International Conference on Computing, Power and Communication Technologies (GUCON), kulalampur, Malayasia (2021)
  2. TCAD Assessment Based Device to Circuit-Level Performance Comparison Study of Source Pocket Engineered All-Si Vertical Tunnel FET and GaSb/Si Heterojunction Vertical Tunnel FET- M. R. Tripathy, A. K. Singh, and S. Jit - 2020 IEEE 17th India Council International Conference (INDICON), New Delhi, India, 1-5 (2020)
  3. Impact of Temperature on DC and AC Characteristics of Stacked Oxide SiO 2 /HfO 2 Cylindrical Gate Tunnel FETs- P. K. Singh, K. Baral, S. Kumar, M. R. Tripathy, A. K. Singh, R. K. Upadhyay, and S. Jit - 2020 IEEE International Conference on Emerging Electronics (ICEE), New Delhi, India(2020)
  4. Influence of Temperature on Analog/Radio Frequency Appearances of Heterojunction Cylindrical Gate Tunnel FETs- P. K. Singh, K. Baral, A. K. Singh, M. R. Tripathy, R. K. Upadhyay, A. P. Singh, and S. Jit - 2020 IEEE International Conference on Computing, Power and Communication Technologies (GUCON), New Delhi, India, 511-515 (2020)
  5. Subthreshold Swing Modeling of Gaussian Doped Double-Gate MOSFETs and its Validation Based on TCAD Simulation- P. K. Singh, K. Baral, S. Kumar, A. K. Singh, M. R. Tripathy, R. K. Upadhyay, and S. Jit- 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, India, 1-4 (2020)
  6. Device and Circuit-Level Performance Comparison of Vertically Grown All-Si and Ge/Si Hetero-Junction TFET- M. R. Tripathy, A Samad, A. K. Singh, P. K. Singh, K. Baral, and S. Jit - 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, India, 1-6 (2020)
  7. Ferroelectric Gate Heterojunction TFET on Selective Buried Oxide (SELBOX) Substrate for Distortionless and Low Power Applications- A. K. Singh, M. R. Tripathy, K. Baral, P. K. Singh, and S. Jit - 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Penang, Malaysia (2020)
  8. Performance Comparison of Ge/Si Hetero-Junction Vertical Tunnel FET with and Without Gate-Drain Underlapped Structure with Application to Digital Inverter- M. R. Tripathy, A. K. Singh, A Samad, K. Baral, P. K. Singh, and S. Jit - 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Penang, Malaysia (2020)
  9. Device-Level Performance Comparison of Some Pocket Engineered III-V/Si Hetero- Junction Vertical Tunnel Field Effect Transistor- M. R. Tripathy, A. K. Singh, S. Chander, P. K. Singh, K. Baral, and S. Jit - 2020 5th International Conference on Devices, Circuits, and Systems (ICDCS), Coimbatore, India, 180-183 (2020)
  10. Study of Temperature Sensitivity on Linearity Figures of Merit of Ge/Si Hetero-Junction Gate-Drain Underlapped Vertical Tunnel FET with heterogeneous gate dielectric structure for Improving Device Reliability- M. R. Tripathy, A. K. Singh, K. Baral, P. K. Singh, A. K. Mishra, D. K. Jarwal, and S. Jit- 2020 URSI Regional Conference on Radio Science (URSI-RCRS), Varanasi, India, 1-4 (2020)
  11. Design and Investigation of Lateral HfO2/SiO2 Gate Stacked TFET on SELBOX Substrate for Low Power and High-Frequency Applications- A. K. Singh, M. R. Tripathy, K. Baral, P. K. Singh, and S. Jit - 2020 URSI Regional Conference on Radio Science (URSI-RCRS), Varanasi, India, 1-4 (2020)
  12. Performance Investigation of a p-Channel Hetero-Junction GaN Tunnel FET- M. R. Tripathy, A. K. Singh, A Samad, S. Chander, P. K. Singh, K. Baral, D. K. Jarwal, A. K. Mishra, and S. Jit - 2019 IEEE MTT-S International Microwave and RF Conference (IMaRC), Mumbai, India, 1-4 (2019)
  13. Study and Investigation of DC and RF Performance of TFET on SEL-BOX and Conventional SOI TFET with SiO2/HfO2 Stacked Gate Structure- A. K. Singh, D. Barah, M. R. Tripathy, K. Baral, S. Chander, P. K. Singh, and S. Jit - 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), Kolkata, India, 1-5 (2019)
  14. Impact of Gate Dielectrics on Analog/RF Performance of Double Gate Tunnel Field Effect Transistor- P. K. Singh, K. Baral, S. Chander, S. Kumar, M. R. Tripathy, A. K. Singh, and S. Jit - 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), Kolkata, India, 1-5 (2019)
  15. Dual Material-Stacked Hetero-Dielectric-Junctionless Accumulation Mode Nanotube MOSFET for enhanced Hot Carrier and Trapped Charges Reliability- K. Baral, P. K. Singh, S. Kumar, S. Chander, M. R. Tripathy, and S. Jit - 2019 Electron Devices Technology and Manufacturing Conference (EDTM), Singapore, 330-332 (2019)
  16. DC and RF Performance Optimization of Strained Si/Si1-xGex Heterojunction SOI P-TFET- A. K. Singh, M. R. Tripathy, P. K. Singh, K. Baral, S. Chander, and S. Jit - 15th IEEE India Council International Conference (INDICON), Coimbatore, India, 1-5 (2018)
  17. Efficient VLSI Implementation of CORDIC-Based Direct Digital Synthesizer- N. Prasad, M. R. Tripathy, A. D. Das, N. R. Behera, A. Swain - Intelligent Computing, Communication and Devices 2014 (Advances in Intelligent Systems and Computing), 308, New Delhi, India (2015)

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