Recent Trends and Developments in Energy-Efficient and Secure Chip Design for IoT Edge Computing

March 18 - 22, 2024

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About SRM University-AP

SRM University-AP is a multi-stream research-intensive university established in 2017 with a focus on diverse fields from Engineering to Sciences and Liberal Arts to Management. Department of Electronics and Communication Engineering aims to impart quality and value-based education to the students/researchers to meet the growing challenges in the industry. The students carry out multidisciplinary research to solve societal problems using state-of-the-art technology.

About the Programme

The FDP is a 5-day programme conducted in hybrid mode with live lectures, hands-on and interactive sessions. The programme will consist of keynote lectures, technical sessions, panel discussions, and hands-on training modules. The technical sessions will include presentations from experts in academia and industry on the latest advancements in the themes mentioned. The panel discussions will provide an opportunity for the participants to interact with the experts and discuss the challenges and opportunities in the emerging fields. The hands-on training will lay a pathway to get real-time knowledge about nanoscale IC design.

Objectives

  • Enhance the knowledge and skills of the participants in designing Analog, Digital, RFIC, and SOC with CMOS scaling for IoT edge Computing.
  • Familiarise every participant with the latest trends and advancements in Nanoscale IC design for AI/ML applications for IoT edge Computing.
  • Familiarise every participant with the latest trends and advancements in neuromorphic and In-memory computing architectures.
  • Enhance the knowledge and skills of the participants in designing hardware security modules, primitives, and lightweight cryptography.

Themes

  • Analog IC Design, Digital IC design, Mixed-signal IC design, RFIC Design examples, and design challenges with CMOS scaling for IoT edge computing
  • Nanoscale IC design for AI/ML applications and VLSI accelerators for AI/ML
  • CMOS and NVM based Neuromorphic and in-memory computing architectures
  • CMOS and post-CMOS based Hardware security primitives design, Hardware Trojans, Lightweight cryptography.

Who can Participate?

Faculty members, Researchers, PG Scholars, and Industry professionals from Engineering Colleges / Institutions, Universities, Research institutions, and Industries. The programme is open to participants from all over the world.

Resource Persons

The resource persons for the Faculty Development Programme will be experts from academia and industry who have extensive experience in hardware security, Chip design, IoT edge computing, Energy Efficient VLSI design.

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