Associate Professor

Dr. Vaddi Ramesh

Department of Electronics and Communication Engineering

Interests

  1. Energy Efficient Circuit Design with Post-CMOS Devices
  2. Hardware Security for IoT
  3. VLSI Accelerators and In-memory Computing Architectures for AI based Edge Devices

Education

2011

Indian Institute of Technology
Roorkee
Ph.D

2004

MANIT Bhopal, Madhya Pradesh,
India
M.Tech

2002

MVGR College of Engg, Vizianagaram,
JNTU Hyderabad
B. Tech

Experience

    • 06/2019- Till Date, Associate Professor, Electronics and Communication Engineering | Department, School of Engineering and Applied Sciences, SRM University, Amaravati, Guntur, AP, India
    • 06/2018- 05/2019, Senior Research Fellow, School of Computing, National University of Singapore, Singapore.
    • 6/2015-05/2018, Assistant Professor, Electronics and Communication Engineering, DSPM International Institute of Information Technology-Naya Rapur Chhattisgarh, India.
    • 1/2014-06/2015, Assistant Professor, Electrical Engineering Department, School of Engineering, Shiv Nadar University, Greater Noida, UP, India.
    • 2/2013- 08/2013, Postdoc Scholar, Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA, USA.
    • 6/2012-1/2013, Professor, Electronics and Communication Engineering Department, Padmasri Dr. B. V. Raju Institute of Technology (BVRIT), Hyderabad, India.
    • 2/2011-4/2012, Postdoctoral Research Fellow, VIRTUS (IC Design Centre of Excellence), Circuits and Systems Division, School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore.
    • 8/2005-12/2007, Assistant Professor, Electronics and Communication Engineering Department, College of Engg, GITAM University, Vizag, India.
    • 7/2004-8/2005, Lecturer (Ad-hoc), Electronics and Communication Engineering Department, Maulana Azad National Institute of Technology, Bhopal, India

Research Interest

  • Energy Efficient Logic and Memory Design with Post-CMOS device Technologies for Next generation Computing platforms and In-Memory computing architectures
  • Energy Efficient power management Circuits and Hardware security circuits for IoT
  • VLSI Accelerators, Reconfigurable Architectures and Approximate Computing Circuits for energy efficient processing of Deep Neural Networks on AI Edge devices

Short Visits Abroad during Summer

  • May-2012- ECE Department, Missouri University of Science and Technology, Rolla, USA
  • August, 2010- ECE Department, HongKong University of Science and Technology (HKUST), HongKong

Awards & Fellowships

  • February, 2016- Inventor Incentive Award- Penn State University, USA
  • April, 2016- Inventor Incentive Award- Penn State University, USA
  • 2008- PhD Scholarship- MHRD
  • 2002- PG Scholarship- MHRD

Memberships

Society Offices, Activities, and Membership:
  • IETE Fellow, Since 2019- Till Date.
  • IEEE Senior Member, 2016- Till Date.
  • IEEE Member, 2012-16.
  • IEEE Student Member, 2008 –11.
  • Member, IEEE Electron Devices Society since 2011
  • Member, IEEE Solid State Circuits Society since 2012.
  • Member, IEEE Circuits and Systems Society since 2017.
Organization and Chairmanship of Technical Sessions, Workshops and Conferences:
  • Session Chair at TEQIP sponsored National Conference on VLSI, Communication and Computing at National Institute of Technology, Bhopal, India, 9th, Dec 2017
  • Coordinator, IEEE SKEP event at IIIT-NR and sponsored by IEEE Bombay section, October 22-23, 2016.
  • Co-ordinated several Training sessions on Cadence, Synopsys, Xilinx Vivado, OrCAD, Multisim, PCB Design tools, etc, at IIIT-NR, 2015-17.
  • Co-coordinator, Two day Faculty Development programme on Analog Circuit Design Using Cadence Tools, Centre for VLSI Design, BVRIT, Hyderabad, India (Jan 4 & 5, 2013).
  • Session Co Chair, Analog and Mixed signal VLSI Design, IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (Prime Asia), Hyderabad, India, Dec, 2012.
  • Session Chair, Embedded systems, NCCI, Hyderabad, India (Dec, 2012).
Member of Technical Program Committees:
  • IEEE International Symposium on Smart Electronic Systems (IEEE-iSES, formerly IEEE-iNIS), 2019.
  • IEEE/VSI VLSI Design and Test Symposium (VDAT), India, 2019.
  • IEEE/VSI VLSI Design and Test Symposium (VDAT), India, 2018.
  • IEEE/VSI VLSI Design and Test Symposium (VDAT), India, 2017.
  • IEEE INDOCON Conference, Dec 15-17, 2017.
Technical Journal or Conference Referee Activities:
  • Mentioned in Golden List of Reviewers for IEEE Electron Devices Letters, Vol.38, No.12, Dec. 2017.
  • Mentioned in Golden List of Reviewers for IEEE Trans. Electron Devices, Vol.64, No.12, Dec. 2017.
  • Mentioned in Golden List of Reviewers for IEEE Trans. Electron Devices, Vol.63, No.12, Dec. 2016.
  • IEEE Trans. on VLSI systems
  • IEEE Trans. on BioCAS
  • IEEE Electron Devices Letters
  • IEEE Trans. On Electron Devices
  • IEEE Trans. on Nanotechnology
  • Elsevier Microelectronics Journal
  • Journal of Applied Physics
  • IOP Semiconductor Science and Technology
  • IEEE International conferences such as ISCAS, DAC, ISLPED, VDAT, ICM, ICCCIT, INDICON, IMPAT, etc.
Invited Talks and Tutorials
  • Resource person for an FDP on Recent Trends in IC Design at Narasaraopeta Engineering College, Guntur, 22nd Nov, 2019.
  • Keynote Speaker at TEQIP sponsored National Conference on VLSI, Communication and Computing at National Institute of Technology, Raipur, India, 9th, Dec 2017.
  • Special Session Speaker on “Tunneling Field Effect Transistors for Energy Efficient Logic, Sensor Interface and 3D IC Circuits for IoT Platforms”, at 3rdIEEE Comp. Society and TVLSI sponsored International Symposium on Nanoelectronic and Information Systems (INIS), Bhopal, India, 18-20, Dec 2017.
  • Sept 26-30, 2016: Invited Speaker and delivered 4 Guest Lectures at TEQIP Workshop on "VLSID SOC & Micro-Nano Technologies", National Institute of Technology (NIT)-Raipur, India.
  • Tutorial Speaker (Half day tutorial along with Prof. S. Dasgupta from IITR),(Topic: Design and Performance Benchmarking of Low Voltage Digital and Analog Circuits with Multi-Gate devices and Tunnel FETs) at IEEE 18th Int. Symp. on VLSI Design and Test (VDAT), Coimbatore, India (16-18 July, 2014).
  • Keynote speaker, on Trends in Emerging nanoscale device technologies for ultra-low power circuit design at 4thNational conference on Recent Trends in Advanced Computing, Electronics and Information Technology, Shobhit University, Meerut, India, 2nd March 2014.
  • Tutorial Speaker (Half day tutorial along with Prof. S. Dasgupta from IITR), IEEE Asia Pacific Conference on Microelectronics (PrimeAsia), (Emerging Device and Circuit design solutions for Energy efficient systems in Nano Scale Technologies), organized in BITs, Hyderabad, (CAS&EDS joint chapter), India (Dec, 2012).
  • Talk on Energy harvesting for Microwatt applications, at GITAM University, Hyderabad campus, India during NCCI (Dec, 2012).
  • Talk on Emerging Device and Circuit Techniques for ultra-low power logic and memory in the nano scale technologies, Missouri University of Science and Technology, Rolla, Missouri, USA (May, 2012).
Student Achievements Under My Supervision:
  • Submitted 4 Designs/Ideas to DST& TI Innovation Call, Sept-2017 and Two got selected for Semi-Finals. (Food Quality tester and Smart dustbin), (2017).
  • Second Year IIITNR ECE students Prakash, Ajeet and Shreya and T. Naga Teja (JRF) for their design on "CMOS Digital LDO Design" done as part of 4th sem VLSI Course project work has been shortlisted in the first round of India Cadence Design Contest, UG category, May, (2017).
  • IIITNR UG 2nd year students Hansa and Nayanika and PhD student Aditya Japa’s are the finalists design for their design on "Smart Girl's security system" at a Prestigious IEEE 30th Int. Conf. on VLSI Design and 16th Int. Conf. on Embedded Systems, Hyderabad, India, 7-11 Jan, (2017).
  • 2nd Prize in Design Contest (Runner up and 25,000Rs cash prize) at 28th IEEE VLSI Design conference, Bangalore, India, 3-7thJan (2015). (PG Student: Siva Nageswar Rao)
  • 2nd Prize in India level Cadence Design Contest, Bangalore, (2015) on “Low Noise and Low power CMOS Neural Amplifier Design, (UG student: Gauri Punekar).
  • Three (Gauri Punekar, Varshine and Geethika) amongst Six Finalists are from my research group in UG category, India level Cadence Design Contest, Bangalore, (2015).
  • Varun Vaid, and Ramesh Vaddi, “Design and Performance Benchmarking of Low Voltage Digital and Analog Circuits with Steep-Slope Devices”, IEEE CAS organized poster session on Microelectronic Circuits, IIT Roorkee, 18-18, Oct, (2014).
  • K. Shravya Reddy, and Ramesh Vaddi, “Robust and Ultra low power subthreshold SRAM design using alternative bit cells”, IEEE VLSI Design conference, Pune ,India, Jan, (2013) (Selected for Design Contest and poster presentation).
  • Japa Aditya, Vallabhaneni Harshita and Ramesh Vaddi “Design Insights and Benchmarking of Hetero Junction Tunnel FET based Energy Efficient Logic Gates”, IEEE International Conference on VLSI Design, at IIT Bombay, India, Jan, (2014) (Selected for Design Contest and poster presentation).

Publications

External Research Projects/Grants Completed:

1. Title: Design, Analysis and Performance Benchmarking of Energy Efficient Hetero Junction Tunnel FET based Digital, Analog, RF Building Blocks (IIIT Naya Raipur)

Role: Principle Investigator

Duration: July 2015 - May 2018

Funding Agency: Department of Science and Technology (DST) SERC Young

Scientist Grant

Value: 24,67,000 INR

Patents:
  • 1. Huichu Liu, Ramesh Vaddi, Suman Datta, and Vijay Narayanan, Power Rectifier using Tunneling Field effect transistor, USA Patent App. No. 14/456,303, Filed on Aug, 2014, Issued with patent No. US 9,391, 068 B2, On July 12, (2016).
  • 2. Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta, Moon Seok Kim, Xueqing Li, Alexandre Schmid, Mahsa Shoaran, Unsuk Heo, Low Power Nano electronics , USA Patent 20150333534, (2015).
Book Chapters
  • 1. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Effect of Independent Gate, Asymmetric and Gate-S/D Underlap features on Nano Scale Subthreshold Double Gate MOSFET Performance, Advances in Microelectronics and Photonics, Nova Science Publishers, (2011).
  • 2. Aditya Japa, Naga Teja, and Ramesh Vaddi, Tunneling Field Effect Transistors for Energy Efficient Digital, RF and Power Management Circuits Design for IoT Edge Computing Devices, IET Book on ‘VLSI and Post-CMOS Devices, Circuits and Modelling, Aug, (2019).
Journal Publications:
  • 1. Japa Aditya, Manoj Kumar Majumder, Subhendu K. Sahoo, and Ramesh Vaddi, Tunnel FET Ambipolarity based Energy Efficient and Robust True Random Number Generator against Reverse Engineering Attacks , Journal of IET Circuits, Device and Systems, March, (2019).
  • 2. Sadulla Shaik, K Sri Rama Krishna and Ramesh Vaddi, Tunnel Transistor Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD , Journal of Circuits, Systems, and Computers, (2017).
  • 3. Sadulla Shaik, K Sri Rama Krishna and Ramesh Vaddi, Nano Scale Transistors with Circuit Interaction for Designing Energy Efficient and Reliable Adder Cells at Low VDD , Journal of IETE Technical Review (Taylor & Francis) , pp.1-12, June, (2017).
  • 4. Japa Aditya, V Harshita, and Ramesh Vaddi, Reliability Analysis of a Tunnel Transistor based Ultra low power Ring Oscillator Design with Circuit Interaction , Journal of IET Circuits, Device and Systems, Vol10, Issue 6, pp.522-527, Nov, (2016).
  • 5. Huichu Liu, Xueqing Li, Ramesh Vaddi, Kaisheng Ma, Suman Datta, and Vijaykrishnan Narayanan, Tunnel FET RF Rectifier Design for Energy Harvesting Applications, Special issue in IEEE Journal on Emerging and Selected Topics in Circuits and Systems,Vol.4, No.4,pp. 400-411, Dec, (2014).
  • 6. Shravya Reddy, and Ramesh Vaddi, Alternative Bit-cell Topologies with Architecture Co-Design for Energy Efficient Nano Scale SRAM”, Special Issue on “Emerging Device and Circuit Techniques for ultra low power memory and logic in the nano scale technologies, Journal of Microelectronics and Solid State Electronics, Scientific & Academic Publishing,Vol.2, Number 2A, pp.22-26, Apr, (2013).
  • 7. Ramesh Vaddi, V. Pott, G. Chua, J. Lin, and T. Kim, Design and Scalability of a Memory Array Utilizing Anchor-free Nano-electro-mechanical Non-volatile Memory Device, IEEE Electron Devices Letters, Vol. 33, No.9,pp. 1315-1317, Sept, (2012).
  • 8. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Compact Modeling of a Generic Double gate MOSFET for subthreshold operation, IEEE Tran. on Electron Devices, Vol. 59, No.10, pp. 2846-2849, Oct. (2012).
  • 9. Vincent Pott, Ramesh Vaddi, G. Chua, J. Lin, and T. Kim, Design optimization of a pulsed-mode electromechanical non-volatile memory, IEEE Electron Devices Letters, Vol. 33, No.8,pp. 1207-1209, Aug (2012).
  • 10. Vincent Pott, Ramesh Vaddi, Julius Tsai Ming Lin, and Tony T. Kim, The shuttle nano-electro-mechanical non-volatile memory, IEEE Tran. on Electron Devices, Vol. 59, pp. 1137-1143, Apr. (2012).
  • 11. Ramesh Vaddi, R. P. Agarwal, S. Dasgupta, and T. Kim, Design and Analysis of Double-gate MOSFETs for Ultra-low Power Radio Frequency Identification (RFID): Device and Circuit Co-design, Journal of Low Power Electronics and Applications, pp. 277-302, July, (2011).
  • 12. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options, Elsevier Microelectronics Journal, Vol.42, Issue 5, pp.798-807, May, (2011).
  • 13. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Comparison of nano-scale complementary metal-oxide semiconductor and 3T–4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic, Journal of IET Circuits, Devices & Systems , Vol. 4, Issue. 6, pp. 548–560, Nov.(2010).
  • 14. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Robustness Comparison of DG-FinFETs with Symmetric, Asymmetric, Tied and Independent gate options with circuit Co-Design for Ultra Low Power Subthreshold Logic, Elsevier Microelectronics Journal ,Volume 41,Issue 4, pp. 195-211, April 2010.
  • 15. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs, ASP Journal of Low Power Electronics (JOLPE), Vol. 6, No 1, pp.103-114, April 2010.
  • 16. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Device and Circuit Co-Design Robustness Studies in the Sub-threshold Logic for Ultra Low Power Applications for 32nm CMOS, IEEE Tran. on Electron Devices, Vol.57, No.3, pp.654-664, March 2010.
  • 17. Ramesh vaddi, S. Dasgupta, R. P. Agarwal, Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultra- Low Power Applications, VLSI Design Journal, Hindawi Publishing corporation, New York, USA, Vol.2009, Article No. 1, January (2009).
International Conferences Outside India:
  • 1. Minh, Ramesh Vaddi, and Weng Fai, Multi-objective Precision Optimization of Deep Neural Networks for Edge Devices , 19th IEEE Design Automation and Test in Europe (DATE), Florence, Italy, March, 25-29, (2019).
  • 2. Palagani Yellappa, Gauri Punekar, Venkateswarlu Gonuguntla, Jun Rim Choi, Ramesh Vaddi, A Novel Design of an Open-loop Configured Low Power and Low Noise CMOS Neural Recording Amplifier, ISOCC, Degeu, South Korea, 12-15 Nov, (2018).
  • 3. Japa Aditya, Naga Teja, and Ramesh Vaddi, Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities, IEEE International Symposium on Circuits and Systems (ISCAS), Italy, May 27-30, (2018).
  • 4. Naga Teja, and Ramesh Vaddi, Energy Efficient and High Throughput Transceiver Design in the Capacitive Coupling Mode Exploring Tunnel Transistors for 3D ICs, 14th IEEE International SOC Conference (ISOCC), Seoul, South Korea, 5-8, Nov, (2017).
  • 5. Sudha Vani, Usha Rani, and Ramesh Vaddi, A Low Voltage Capacitor Based Current Controlled Sense Amplifier for Input Offset Compensation, 14th IEEE International SOC Conference (ISOCC), Seoul, South Korea, 5-8, Nov, (2017).
  • 6. G. Kaushal, Subramanyam K, Shiva Nageswar Rao, Vidya K,.Radhika Ramya, Sadulla Shaik, H Jeong, Seong-Ook Jung, and Ramesh Vaddi, Design and Performance Benchmarking of Tunnel FET based Low Voltage Digital and Analog Circuits Enabling Self-powered SOCs, 11th IEEE Int. SOC Design Conference, Korea, Nov 3-6, (2014).
  • 7. H. Liu, Ramesh Vaddi, S. Datta, and V. Narayanan, Tunnel FET based Ultra-Low Power, High Sensitivity UHF RFID Rectifier, IEEE International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, (2013).
  • 8. Ramesh Vaddi, Vincent Pott, Julius Tsai Ming Lin, and Tony T. Kim, Design and Analysis of Anchorless Shuttle Nano-electro-mechanical Non-volatile Memory for High Temperature Applications, IEEE Int. Reliability Physics symposium (IRPS), Anaheim, CA, USA, April, (2012).
  • 9. Ramesh Vaddi, Vincent Pott, Julius Tsai Ming Lin, and Tony T. Kim, Design, Modeling and Simulation of an Anchorless Nano-Electro- Mechanical Nonvolatile Memory, International Conference on Solid-State and Integrated Circuit (ICSIC), Singapore, March (2012).
  • 10. Ramesh Vaddi, and Tony T. Kim, Ultra-low Power High Efficient Rectifiers with 3T/4T Double-gate MOSFETs for RFID Applications, Proc. IEEE International Symposium on Integrated Circuits (ISIC), Singapore, Dec 12-14, (2011).
  • 11. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Two Dimensional Analytical Subthreshold Swing Model of a Generic (3T- 4T) Double Gate MOSFET with Gate-S/D Underlap, Proc. IEEE Int. conference on Electronic Devices, Systems and Applications (ICEDSA), Kuala Lumpur, Malaysia, pp. 246-249, 25 - 27 April (2011).
  • 12. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Two Dimensional Analytical Subthreshold current Model of a Generic (3T- 4T) Double Gate MOSFET with Gate-S/D Underlap, Proc. IEEE Int. conference on Electronic Devices, Systems and Applications (ICEDSA), Kuala Lumpur, Malaysia, pp. 67-72, 25 - 27 April (2011).
  • 13. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Analytical Potential Distribution Model for Underlap Double Gate MOSFETs with 3T-4T and Symmetric- Asymmetric Options for Subthreshold operation: A Conformal Mapping Approach, Proc. Of Nanotech Conf& Expo (NSTI), Anaheim, California, USA, Vol.2, pp. 697-700, 21-24, June (2010).
International Conferences held in India:
  • 1. Naga Teja, JapaAditya, and Ramesh Vaddi, Tunneling Field Effect Transistors for Energy Efficient Logic, Sensor Interface and 3D IC Circuits for IoT Platforms, 3rd IEEE International Symposium on Nanoelectronic and Information Systems (IEEE-iNIS), Bhopal, India, 18-20, Dec (2017).
  • 2. JapaA ditya, V. Harshita, and Ramesh Vaddi, Exploiting Characteristics of Steep Slope Tunnel Transistors towards Energy Efficient and Reliable Buffer Designs for IoT SoCs, 21st IEEE/VSI sponsored VLSI Design and Test Symposium (VDAT), IIT Roorkee, India, 29th June- 2nd July, (2017).
  • 3. Sudha vani Yamani, Usha Rani Nelakuditi and Ramesh Vaddi, Low Write Energy STT-MRAM Cell using 2T- Hybrid Tunnel FETs exploiting the Steep slope and Ambipolar characteristics, 21st IEEE/VSI sponsored VLSI Design and Test Symposium (VDAT), IIT Roorkee, India, 29th June- 2nd July, (2017).
  • 4. Aditya Japa, Sadulla Shaik, and Ramesh Vaddi, Exploiting the Steep Subthreshold Slope Characteristics of Tunnel Transistors for Wide Tuning Range Voltage Controlled Ring Oscillator (VCRO) Design at Scaled Supply Voltages Down to 150mV, Electron Devices Society sponsored IEEE Int. Conference on Emerging Electronics, IIT Bombay, India, Dec.27-30, (2016).
  • 5. Varshine Kolla, Naga Teja, and Ramesh Vaddi, Robust and Energy Efficient Non-Volatile Reconfigurable Logic Circuits with Hybrid CMOS-MTJs, Electron Devices society sponsored IEEE Int. Conference on Emerging Electronics, IIT Bombay, India, Dec.27-30, (2016).
  • 6. Sadulla Shaik, K Sri Rama Krishna and Ramesh Vaddi, Circuit and Architectural Co-Design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing, 29th IEEE Int. Conf. on VLSI Design, Coimbatore, India, 4-6 Jan, (2016).
  • 7. Sadulla Shaik, K Sri Rama Krishna and Ramesh Vaddi, Tunnel Transistors with Circuit Co-Design in Designing Reliable Logic Gates for Energy Efficient Computing, 6th IEEE ‘Int. CAS/EDS Conf. On. Post-Graduate Research in Microelectronics and Electronics (Prime Asia)’, Hyderabad, India, 27-29th Nov, (2015).
  • 8. Subramanyam, Sk. Sadulla and Ramesh Vaddi, Tunnel FET based Low Voltage Static vs Dynamic Logic Families for Energy Efficiency, IEEE 18th Int. Symp. on VLSI Design and Test (VDAT), Coimbatore, India, 16-18 July, (2014).
  • 9. JapaAditya, Vallabhaneni Harshita and Ramesh Vaddi, Design Insights and Benchmarking of Hetero Junction Tunnel FET based Energy Efficient Logic Gates, IEEE International Conference on VLSI Design, IIT Bombay, India, Jan, (2014) (Selected for Design Contest and poster presentation).
  • 10. V. Harshita, J. Aditya, Sk.Sadulla, K.Sri Rama Krishna and Ramesh Vaddi, Designing Energy Efficient Logic Gates with Hetero Junction Tunnel FETs at 20nm, IEEE Trans. On Electron Devices sponsored Device, Circuit, System Conference (ICDCS), Coimbatore, India, March (2014).
  • 11. K. Shravya Reddy, and Ramesh Vaddi, Robust and Ultra low power subthreshold SRAM design using alternative bit cells, IEEE VLSI Design conference, Pune ,India, Jan, (2013) (Selected for Design Contest and poster presentation).
  • 12. Ramesh Vaddi, and S.Dasgupta, Enhanced Bias flip rectifier with ultra low power control circuitry for Piezoelectric Energy harvesting, IEEE Asia-Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia), Hyderabad, India, Dec (2012).
  • 13. Ramesh Vaddi, S. Dasgupta, and R.P. Agarwal, Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET, Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IIT Madras, India, pp.37-42, July 4-6, (2011).
  • 14. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Robustness to PVT variations of Nano Scale Subthreshold CMOS Logic for Ultra Low Power Application, Proc. Of International Conference on convergence of science and Engineering in Education and Research (ICSE-2010), Bangalore, India, (2010).
  • 15. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Robustness Comparisons of bulk CMOS and DGFinFET technologies with Circuit Co-Design for Energy Efficient Subthreshold Logic, IEEE International workshop on the Physics of Semiconductor Devices (IWPSD), New Delhi, India, Dec. (2009).
  • 16. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Investigation of Robustness and Performance Comparisons of DG-FinFETs with Symmetric, Asymmetric, Tied and Independent gate options for Optimal Subthreshold Logic, 4thIEEE International Conference on Computers & Devices for Communication (CODEC), Kolkata, India, (2009).
  • 17. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, SDG vs ADG with Tied and Independent gate Options in the Subthreshold Logic for Ultra Low Power Applications, 2ndIEEE Int. workshop. on Electronic Devices and Semiconductor Technology (IEDST), IIT Bombay, India, June (2009).
National Journals/Conferences:
  • 1. Madhavi Rani, AshaJyothi, Anusha, Anil Kumar and Ramesh Vaddi, Digital Design and Simulation of a Minimum Size FIR Processor, GITAM Journal of Information Communication Technology (GJICT), (2008).
  • 2. Ramesh Vaddi, Madhavi Rani, AshaJyothi, VHDL Modeling and Simulation of minimum size FIR Processor, National conference on Emerging trends in ECE (Ncemerge-07), JNTU Anantapur, India, (2007).
  • 3. Ramesh Vaddi, S.S. Rathod, Analysis of Dynamic behavior of a Diode for Switching applications using HSPICE Simulations, National conference on Emerging trends in Communication (ETC-2K9), SVIET, Chandigarh, India, Feb 20-21, (2009).
  • 4. Ramesh Vaddi, S.Dasgupta, Device and Circuit performance studies with Technology scaling for Superthreshold operation using Hspice Simulations, National conference on Emerging trends in Communication (ETC-2K9), SVIET, Chandigarh, India, Feb 20-21, (2009).
  • 5. Ramesh Vaddi, S. Dasgupta and R.P. Agarwal, Nano scale Device and Circuit Design Challenges with Technology Scaling for Robust and Low Power VLSI, National Conference on Emerging Trends in Advanced Computing & Informatics (CICON), Meerut, India, May 8- 9, (2010).

Contact Details

  • E-mail id: ramesh.v@srmap.edu.in
  • Mobile No.:
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