Assistant Professor

Dr Indranil Hatai

Department of Electronics and Communication Engineering

Interests

  1. Reconfigurable Architectural Design of ICs
  2. Artificial Intelligent/Machine Learning Hardware
  3. Edge Computing Hardware Design

Education

2004

University of Burdwan,
India
BE

2011

Indian Institute of Technology Kharagpur,
India
MS by Research

2017

Indian Institute of Technology Kharagpur,
India
PhD

Experience

  • 1st January 2020 to 2nd May 2021 - Adjunct Professor - MIIT Myanmar
  • 29th october 2018 to 31st December 2019 - Research Fellow - NUS Singapore
  • 30 July 2015 to 28th October 2018 - Assistant Professor (Contractual) - IIEST Shibpur

Research Interest

  • Fabrication and characterization of 2D layered transition metal dichalcogenides (TMDs), Oxides (TMOs) and Carbides (Mxenes) leading to device applications i.e. FETs, Solar Cells and Energy storage. Epitaxial growth of Metal and Semiconductor hetero-structures and their characterizations.
  • Crystallographic texture analysis by X-ray pole figure and RHEED surface pole figure techniques.

Awards & Fellowships

  • Offering online course on “Architectural Design of Digital Integrated Circuit design” in NPTEL online MOOC course for two session 2018 and 2020, 2021
  • 3rd Student Best Paper Award in Advances in 2nd International Conference on Electrical Engineering (ICAEE), Dhaka, Bangladesh December 2013
  • One of the final 20 team among 120 teams from all-over India in Coreel Digilent Design Contest (CDDC-2013)
  • Winner of the Best Engineering Student award in the Electronics Engineering category in Supreme Engineers Award-2012
  • One of the top 5 member of the Cadence Design Contest 2011 in Master’s Category Winners of the Cadence Design Contest 2010 in Master’s Category
  • Best paper award in IEEE 2011 Students Technology Symposium (TechSym 2011), 14-16 January 2011, IIT Kharagpur, India
  • Best paper award in First International conference on VLSI Design & Communication Systems (ICVLSICOM-10), 8-10 January 2010, Chennai, India
  • 2nd Student Best Poster Paper Award in 4th International Conference on Computers and Devices for Communication (CODEC-09) Kolkata, India 14-16 December 2009

Memberships

  • IEEE Student Membership

Publications

BOOK
  • “FPGA Implementation of a Reconfigurable Baseband Modem for SDR System: Reconfigurable Multi-Standard Baseband Modulator and Demodulator Design”, LAP Lambert Academic Publishing AG & Co KG (23 April 2012)
BOOK CHAPTER
  • “A high-speed, low-power, low-latency pipelined ROM-less DDFS”, in Advanced Computing book of Springer Book series on Communications in Computer and Information Science, Springer Berlin Heidelberg, 2011
INTERNATIONAL JOURNALS
  • I. Hatai, I. Chakrabarti and S. Banerjee, “A Computationally Efficient Reconfigurable Constant Multiplication Architecture based on CSD Decoded Vertical-Horizontal Common
    Sub-Expression Elimination Algorithm”, (IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 1, pp. 130-140, Jan. 2018 (Impact Factor: 3.318)
  • I. Hatai, I. Chakrabarti, S. Banerjee, “An efficient constant multiplier architecture based on vertical-horizontal binary common subexpression elimination algorithm for reconfigurable FIR filter synthesis”, IEEE Transactions on Circuits and Systems-I: Regular Papers, vol.62, no.4, pp.1071-1080, April 2015, doi: 10.1109/ TCSI.2015.2388838 (Impact Factor:3.318)
  • I. Hatai, I. Chakrabarti, S. Banerjee, “An Efficient VLSI Architecture of a reconfigurable Pulse-Shaping FIR Interpolation Filter for Multi-Standard DUC”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.23, no.6, pp.1150-1154, June 2015 doi: 10.1109/TVLSI.2014.2321171 (Impact Factor: 2.037)
INTERNATIONAL CONFERENCES
  • Annapurna Mondal ; Sagnik Bhar ; Supriyo Srimani ; Indranil Hatai ; Kasturi Ghosh ; Hafizur Rahaman , "Analytical Model of a Multi-Resolution Sample rate re-configurable Decimator for SDADC," 2019 IEEE Region 10 Symposium (TENSYMP), Kolkata, India, June 2019, pp. 588-592, doi: 10.1109/TENSYMP46218.2019.8971138”
  • Sagnik Bhar ; Annapurna Mondal ; Supriyo Srimani ; Indranil Hatai ; Subhajit Das ; Kasturi Ghosh ; Hafizur Rahaman, "A low power driver amplifier for Fully Differential ADC, 2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS), Higashi-Hiroshima, Japan, 2019, pp. 1-6, doi: 10.1109/ISDCS.2019.8719267
  • I. Hatai, I. Chakrabarti, S. Banerjee, “ FPGA implementation of a fetal heart rate measuring system”, International Conference on Advances in Electrical Engineering (ICAEE), pp.160-164, Dhaka, Bangladesh, 19-21 Dec 2013 (Won third best paper award) (DOI:10.1109/ICAEE.2013.6750325)
  • I. Hatai, I. Chakrabarti, S. Banerjee, “Reconfigurable architecture of a RRC FIR interpolator for multi-standard digital up converter”, IEEE 27 th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), pp. 247-251, May 20-21, 2013, Boston, U.S.A (DOI: 10.1109/IPDPSW.2013.188)
  • I. Hatai, S. Banerjee, I. Chakrabarti, “Reconfigurable Architecture of a RRC FIR Interpolation Filter for Multi-Standard Digital Up Converter”, International Conference on Advances in Electrical Engineering (ICAEE 2011), 19-21 December, 2011, Dhaka, Bangladesh
  • I. Hatai, I. Chakrabarti, “A Novel Low-Latency, High-Speed DDFS Architecture”, Annual IEEE India Conference (INDICON), pp.1-4, 17-19 Dec.2010 (DOI: 10.1109/INDCON.2010.5712646)
  • I. Hatai, I. Chakrabarti, “A high-speed, ROM-less DDFS for software defined radio system”, IEEE International Conference on Communication Control and Computing Technologies (ICCCCT), pp. 115-119, Chennai, India, 7-9 Oct, 2010 (DOI: 10.1109/ICCCCT.2010.5670538).
  • I. Hatai, R. Biswas, S. Banerjee, “ASIC Implementation of a 512-point FFT/IFFT Processor for 2D CT Image Reconstruction Algorithm”, IEEE Students' Technology Symposium (TechSym), 2011 , pp. 220-225, 14-16 Jan.2011 (won Best paper award) (DOI:10.1109/TECHSYM.2011.5783849)
  • I. Hatai, I. Chakrabarti, "Parameter controlled reconfigurable baseband modulator for SDR architecture," 2 nd International Conference on Mechanical and Electronics Engineering (ICMEE), 2010, vol.1, no., pp.V1-29-V1-33, 1-3 Aug. 2010, Kyoto, Japan (DOI:10.1109/ICMEE.2010.5558602)
  • I. Hatai, I Chakrabarti, “Design and Implementation of a Programmable Baseband Modulator for SDR Architecture”, First International conference on VLSI Design & Communication Systems (ICVLSICOM-10), 8-10 January 2010, Chennai, India (won Best paper award)
  • I. Hatai, I Chakrabarti, “Digital FM Modem for SDR Architecture”, 4 th International Conference on Computers and Devices for Communication (CODEC-09) , pp. 1-4, Kolkata, India 14-16 December 2009 (won Second Best Poster Paper Award) (http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5407205&isnumber=5407062)
  • I. Hatai, I Chakrabarti, “FPGA Implementation of a High Performance Digital FM Demodulator”, International Conference on Modeling and Simulation (MS’09), Trivandrum, Kerala, India 1-3 December 2009
  • Hatai, I Chakrabarti, “FPGA Implementation of a Digital FM Modem”, International Conference on Information and Multimedia Technology, (ICIMT '09), pp.475-479, 16-18, Dec.2009 doi: 10.1109/ICIMT.2009.18

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