Assistant Professor

Dr. Deepak Kachave

Department of Computer Science and Engineering

Interests

  1. VLSI CAD for ensuring Reliability and Security of IP Cores.
  2. Internet of Things
  3. Computer Architecture

Education

2014

RGPV Bhopal
India
B.E.

2019

Indian Institute of Technology, Indore
India
Ph.D

Experience

  • Dec, 2019 – Current – Assistant Professor – SRM University Andhra Pradesh
  • July, 2019 – Dec, 2019 – Assistant Professor – Indian Institute of Information Technology Pune

Research Interest

  • IP Cores: Transient Fault Tolerant IP Cores, Logically Locked/Obfuscated IP Cores, Digital Image Processing based IP Cores, Digital Signal Processing based IP Cores.
  • Automated vehicles, Hardware Accelerators, Computer Architecture, Internet of Things.

Memberships

  • Member – IEEE Internet of Things Community
  • Member – IEEE Consumer Electronics Society
  • Member – IEEE Computer Society Technical Committee on VLSI
  • Member – IEEE Council on Electronic Design Automation

List of Publications

  • Spatial and Temporal Redundancy for Transient Fault Tolerant Datapath, Anirban Sengupta, Deepak Kachave, in IEEE Transactions on Aerospace and Electronic Systems (TAES), 54 (3), 1168-1183 (2018)
  • Low Cost Functional Obfuscation of Reusable IP Cores used in CE Hardware through Robust Locking, Anirban Sengupta, Deepak Kachave, Dipanjan Roy, in IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), 38 (4), 604-616 (2019
  • Fault Tolerant DSP core datapath against Omni-directional spatial impact of SET, Deepak Kachave, Anirban Sengupta, in IEEE Canadian Journal of Electrical and Computer Engineering, 42 (3), 102-107 (2019)
  • Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking, Deepak Kachave, Anirban Sengupta, in IEEE Consumer Electronics, 7 (2), 111-114 (2018)
  • Digital Processing Core Performance Degradation Due to Hardware Stress Attacks Deepak Kachave, Anirban Sengupta, in IEEE Potentials, vol. 38, no.2, pp. 39-45, April 2019
  • Applying digital forensic for hardware protection : resolving false claim of IP ownership, Deepak Kachave, Anirban Sengupta, in IEEE VLSI Circuits & Systems Letter, 4 (1), 10 - 13 (2018)
  • Effect of NBTI Stress on DSP cores used in CE Devices: Threat Model and Performance Estimation, Deepak Kachave, Anirban Sengupta, Shubha Neema, Panugothu Sri Harsha, in IET Journal on Computers & Digital Techniques (CDT), 12 (6), 268-278 (2018)
  • Particle Swarm Optimisation Driven Low Cost Single Event Transient Fault Secured Design during Architectural Synthesis, Anirban Sengupta, Deepak Kachave, in IET Journal of Engineering, 184-194 (2017)
  • Low Cost Fault Tolerance against kc-cycle and km-unit Transient for Loop Based Control Data Flow Graphs during Physically Aware High Level Synthesis, Anirban Sengupta, Deepak Kachave, in Elsevier Journal on Microelectronics Reliability, 74, 88-99 (2017)
  • "Forensic Engineering for Resolving Ownership Problem of Reusable IP Core generated during High Level Synthesis", Anirban Sengupta, Deepak Kachave, in Elsevier Journal on Future Generation Computer Systems, 80, 29-46 (2018)
  • Integrating Physical Level Design and High Level Synthesis for Simultaneous Multi-Cycle Transient and Multiple Transient Fault Resiliency of Application Specific Datapath Processors”, Deepak Kachave, Anirban Sengupta, Elsevier Journal on Microelectronics Reliability, 60, 141-152 (2016)
  • Hardware Reliability Analysis of DSP Cores", Deepak Kachave, Anirban Sengupta, IET Book: VLSI and Post-CMOS Devices, Circuits and Modelling, Invited Book Chapter, 2018
  • Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis, Anirban Sengupta, Deepak Kachave, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, 75-80 (2016)
  • Protecting Ownership of Reusable IP Core Generated during High Level Synthesis, Deepak Kachave, Anirban Sengupta, in IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Gwalior, 80-82 (2016)
  • Reliability and Threat Analysis of NBTI Stress on DSP Cores, Anirban Sengupta, Deepak Kachave, Shubha Neema, Panugothu Sri Harsha, in IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Bhopal, 11-14 (2017)
  • Integrating Compiler Driven Transformation and Simulated Annealing based Floorplan for Optimized Transient Fault Tolerant DSP cores, Anirban Sengupta, Deepak Kachave, in IEEE International Symposium on Smart Electronic Systems (iSES), Hyderabad, 17-20 (2018)

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