Assistant Professor

Dr Deepak Kachave 

Department of Computer Science and Engineering


  1. VLSI CAD for ensuring Reliability and Security of IP Cores.
  2. Internet of Things
  3. Computer Architecture



RGPV Bhopal


Indian Institute of Technology, Indore


  • Dec, 2019 – Current – Assistant Professor – SRM University Andhra Pradesh
  • July, 2019 – Dec, 2019 – Assistant Professor – Indian Institute of Information Technology Pune

Research Interest

  • IP Cores: Transient Fault Tolerant IP Cores, Logically Locked/Obfuscated IP Cores, Digital Image Processing based IP Cores, Digital Signal Processing based IP Cores.
  • Automated vehicles, Hardware Accelerators, Computer Architecture, Internet of Things.


  • Member – IEEE Internet of Things Community
  • Member – IEEE Consumer Electronics Society
  • Member – IEEE Computer Society Technical Committee on VLSI
  • Member – IEEE Council on Electronic Design Automation

List of Publications


  • Anirban Sengupta, Deepak Kachave, "Spatial and Temporal Redundancy for Transient Fault Tolerant Datapath," in IEEE Transactions on Aerospace and Elect+C4:C14ronic Systems (TAES), vol. 54, no. 3, pp. 1168-1183, June 2018. (Impact factor ~2).
  • Anirban Sengupta, Deepak Kachave, Dipanjan Roy "Low Cost Functional Obfuscation of Reusable IP Cores used in CE Hardware through Robust Locking", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), Vol. 38, no. 4, pp. 604-616, April 2019 (Impact factor ~2).
  • Deepak Kachave, Anirban Sengupta, "Fault Tolerant DSP core datapath against Omni-directional spatial impact of SET", in IEEE Canadian Journal of Electrical and Computer Engineering, Accepted February 2019 (Impact factor ~1).
  • Deepak Kachave, Anirban Sengupta, "Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking", in IEEE Consumer Electronics, vol. 7, no. 2, pp. 111-114, March 2018.
  • Deepak Kachave, Anirban Sengupta, "Digital Processing Core Performance Degradation Due to Hardware Stress Attacks", IEEE Potentials, vol. 38, no.2, pp. 39-45, April 2019.
  • Deepak Kachave, Anirban Sengupta, "Applying digital forensic for hardware protection : resolving false claim of IP ownership", IEEE VLSI Circuits & Systems Letter, Volume 4, Issue 1, pp. 10 - 13, Feb 2018.
  • Deepak Kachave, Anirban Sengupta, Shubha Neema, Panugothu Sri Harsha " Effect of NBTI Stress on DSP cores used in CE Devices: Threat Model and Performance Estimation", IET Journal on Computers & Digital Techniques (CDT), 2018.(Impact factor ~0.6).
  • Anirban Sengupta, Deepak Kachave "Particle Swarm Optimization Driven Low Cost Single Event Transient Fault Secured Design during Architectural Synthesis (Invited Paper)", IET Journal of Engineering, p. 184-194, 2017
  • Anirban Sengupta, Deepak Kachave "Low Cost Fault Tolerance against kc-cycle and km-unit Transient for Loop Based Control Data Flow Graphs during Physically Aware High Level Synthesis", Elsevier Journal on Microelectronics Reliability, Volume 74, July 2017, pp. 88-99. (Impact factor ~1.2)
  • Anirban Sengupta, Deepak Kachave "Forensic Engineering for Resolving Ownership Problem of Reusable IP Core generated during High Level Synthesis"", Elsevier Journal on Future Generation Computer Systems, Volume 80, Pages 29-46, March 2018. (Impact factor ~4.6)."
  • Deepak Kachave, Anirban Sengupta, "Integrating Physical Level Design and High Level Synthesis for Simultaneous Multi-Cycle Transient and Multiple Transient Fault Resiliency of Application Specific Datapath Processors", Elsevier Journal on Microelectronics Reliability, Volume 60, Pages 141-152, May 2016. (Impact factor ~1.2).

Conference Papers

  • Anirban Sengupta, Deepak Kachave, "Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis," 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, 2016, pp. 75-80.
  • Anirban Sengupta, Deepak Kachave, Shubha Neema, Panugothu Sri Harsha, "Reliability and Threat Analysis of NBTI Stress on DSP Cores," 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Bhopal, 2017, pp. 11-14.
  • Deepak Kachave, Anirban Sengupta, "Protecting Ownership of Reusable IP Core Generated during High Level Synthesis," 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Gwalior, 2016, pp. 80-82.
  • Anirban Sengupta, Deepak Kachave, "Integrating Compiler Driven Transformation and Simulated Annealing based Floorplan for Optimized Transient Fault Tolerant DSP cores," 2018 IEEE International Symposium on Smart Electronic Systems (iSES), Hyderabad, 2018, (accepted and presented)

Book Chapters

  • Deepak Kachave, Anirban Sengupta, "Hardware Reliability Analysis of DSP Cores", IET Book: VLSI and Post-CMOS Devices, Circuits and Modelling, Invited Book Chapter, 2017

Contact Details

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