Assistant Professor

Dr Adusumilli Vijaya Bhaskar

Department of Computer Science and Engineering

Interests

  1. Computer Architecture
  2. Edge Intelligence
  3. Internet of Things

Faculty Details

Education

2008

JNTU Hyderabad

B.Tech.

2012

JNTU Kakinada

M.Tech.

2022

IIT Madras
India

Ph.D.

Experience

  • Jan 2023 - Jan 2025, Research Fellow, Nanyang Technological University Singapore

Research Interest

  • Study of modern processor architectures and develop robust, advanced architectures suitable for the current and future generations technologies
  • Develop machine learning tools suitable for edge intelligence and internet of things

Publications

  • A. Vijaya Bhaskar, T.G. Venkatesh, Traffic Characterization based Stochastic Modelling of Network-on-chip, April 2023, 10.1109/TC.2022.3191965, IF-3.6, Q1.
  • A. Vijaya Bhaskar, T.G. Venkatesh, Performance analysis of network-on-chip in many-core processors, Journal of Parallel and Distributed Computing, Volume 147, 2021, Pages 196-208, ISSN 0743-7315, https://doi.org/10.1016/j.jpdc.2020.09.013, IF-3.4, Q1
  • Melvin T. Balakrishnan, T.G. Venkatesh, Vijaya Bhaskar, Design And Implementation of Congestion Aware Router for Network-on-Chip, Integration, Volume 88, 2023, Pages 43-57, ISSN 0167-9260, https://doi.org/10.1016/j.vlsi.2022.08.012. IF-2.2, Q3
  • Bala Surendra Adusumilli, Vinod Raj, Vijaya Bhaskar Adusumilli, Capacitor placement and sizing to minimize losses in a radial distribution network considering uncertainty using modified affine arithmetic division, Sustainable Energy, Grids and Networks, Volume 27,2021,100492, ISSN 23524677, https://doi.org/10.1016/j.segan.2021.100492, IF-4.8, Q1
  • A. V. Bhaskar, "A new method of power analysis of Network-on-Chip using analytical modelling"; 2022 Seventh International Conference on Parallel, Distributed and Grid Computing (PDGC), Solan, Himachal Pradesh, India, 2022, pp. 222-227, doi:10.1109/PDGC56933.2022.10053136.
  • A. V. Bhaskar, "Estimation of Power Consumption in a Network-on-Chip Router"; 2022 IEEE Delhi Section Conference (DELCON), New Delhi, India, 2022, pp. 1-7, doi:10.1109/DELCON54057.2022.9753477.
  • A. V. Bhaskar, "A Detailed Power Analysis of Network-on-Chip"; 2022 IEEE Delhi Section Conference (DELCON), New Delhi, India, 2022, pp. 1-7, doi:10.1109/DELCON54057.2022.9752850.
  • B. R. Rayapati, N. Rangaswamy and A. V. Bhaskar, "Energy Efficient VoD with Cache in TWDM PON ring"; 2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP), Vijayawada, India, 2022, pp. 1-5, doi: 10.1109/AISP53593.2022.9760612.
  • Vijaya Bhaskar. 2021. A Study of Network-on-Chip Performance. In 2021 Thirteenth International Conference on Contemporary Computing (IC3-2021) (IC3 '21). Association for Computing Machinery, New York, NY, USA, 37–42. https://doi.org/10.1145/3474124.3474129
  • V. Vutukuri, V. B. Adusumilli, P. K. Uppu, S. Varsa and R. K. Thummala,"Verification of SDRAM controller using SystemVerilog", 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, India, 2020, pp. 1-6, doi:10.1109/CONECCT50063.2020.9198440.
  • R. Akhil, J. R. Koleti, A. Vijaya Bhaskar, V. Sathish and B. A. Goud, "Delay and Area analysis of hardware implementation of FFT using FPGA"; 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, India, 2020, pp. 1-6, doi:10.1109/CONECCT50063.2020.9198617.
  • A. Vijaya Bhaskar, T.G. Venkatesh, A study of the effect of virtual channels on the performance of Network-on-Chip, 2015 IEEE Student Conference on Research and Development (SCOReD), Kuala Lumpur, 2015, pp. 255-260. doi:10.1109/SCORED.2015.7449335

Contact Details

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